In Dynamic Random Access Memory (DRAM) technology wherein a capacitor is used as a storage element, it is necessary to connect the access transistor active area to the capacitor bottom plate (storage plate). This connection is known as a buried contact, i.e., other layers or elements are above the contact surface. Typically, buried contacts are no smaller than the lithographic minimum associated with patterning the wafer.
It is the purpose of this invention to reduce the size of this contact surface for the following reasons: the cell area may be reduced; the capacitor storage plate registration alignment is improved; the soft error rate is improved since there is a smaller buried contact area that intercepts alpha particles; the subthreshold voltage characteristics are improved by moving the buried contact edge away from the access transistor; and it is possible to form the contact as self-aligned in both directions so a single large rectangular mask can be used to etch a plurality of buried contacts.